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Synopsys Inc Patents
What Synopsys Inc has filed at the patent office — applications as well as grants, because a filing is on the record eighteen months before anyone has to say what it was for.
SNPS on carbonthat →Filings on file
53
Granted
8
Still pending
45
Filed under
3 names
53 filings
Newest filing first. A pending application has no patent number yet, and most never get one.
| Invention | Patent |
|---|---|
| DIVIDING A CHIP DESIGN FLOW INTO SUB-STEPS USING MACHINE LEARNINGG06F 30/392, G06F 30/398, G06F 30/31, G06F 30/394, G06F 30/27, G06F 30/327, G06F 30/396Filed as Synopsys, Inc.2025-11-24Amzie Allen Adams | pending |
| MACHINE-LEARNING-AIDED LOGIC SYNTHESIS USING DO-NOT-CARE-BASED BACKPROPAGATIONFiled as SYNOPSYS, INC.2025-11-10YUKIO MIYASAKA | pending |
| GRAPH-BASED VISUALIZATION OF WAYPOINT FOR DETECTING DESIGN ERROR IN INTEGRATED CIRCUIT DESIGNFiled as SYNOPSYS, INC.2025-10-10SUBHADIP HALDER | pending |
| Method for Producing a Technical Object via Implicit and Continuous Numerical simulation of a Complex Multi-Scale Physical Phenomenon by Deep LearningFiled as SYNOPSYS, INC.2025-09-29Louis VERRET | pending |
| METHODS AND SYSTEMS FOR THE ESTIMATION OF THE COMPUTATIONAL COST OF SIMULATIONG06F 30/27, G06N 20/00, G06F 30/23, G06F2111/10, G06N 3/09, G06N 3/048, G06N 3/045, G06N 3/0464, G06N 5/01, G06N 3/08Filed as Synopsys, Inc.2025-08-25Kyle Kosic | pending |
| MACHINE-LEARNING-AIDED LOGIC SYNTHESIS USING DO-NOT-CARE-BASED BACKPROPAGATIONG06N 3/084, G06F 30/327Filed as Synopsys, Inc.2025-08-04Yukio MIYASAKA | pending |
| Circuitry for Staggering Capture Clocks in Testing Electronic Circuits with Multiple Clock DomainsG01R 31/318552, G01R 31/318594, G01R 31/31726, G01R 31/318536, G01R 31/31937Filed as Synopsys, Inc.2025-07-08Bala Tarun Nelapatla | pending |
| GENERATING HARDWARE DESCRIPTION LANGUAGE SLICES TO PROVIDE CONTEXT FOR VIOLATIONSFiled as SYNOPSYS, INC.2025-06-25THANUJA MADUSANKA | pending |
| DYNAMIC CLOCK TREE PLANNING USING FEEDTIMING COSTG06F 30/396, G06F 30/392, G06F 30/3312, G06F 30/398, G06F 30/373, G06F 30/394, G06F 30/337, G06F2119/12Filed as Synopsys, Inc.2025-06-17Vivek Kumar | pending |
| MEMORY CELL NOISE PROTECTION VIA BIDIRECTIONAL THRESHOLD SWITCHING DEVICESFiled as SYNOPSYS, INC.2025-06-04ROUWAIDA KANJ | pending |
| MEASURING DEVICE DEFECT SENSITIZATION IN TRANSISTOR-LEVEL CIRCUITSG01R 31/2848, G06F 30/323, G06F 30/3308, G06F 30/33, G06F 30/3323Filed as Synopsys, Inc.2025-05-21Mayukh BHATTACHARYA | pending |
| DISTRIBUTED TEST PATTERN GENERATION AND SYNCHRONIZATIONG06F 30/398, G01R 31/2834, G06F2115/12, G06F 11/3676, G06F 11/3688Filed as Synopsys, Inc.2025-05-19Peter Wohl | pending |
| VIRTUAL MACHINE EXECUTION WITH HETEROGENOUS HOST AND VIRTUAL MACHINE INSTRUCTION SET ARCHITECTURESFiled as SYNOPSYS, INC.2025-04-18SIMON SCHÖNING | pending |
| BOOLEAN REASONING GUIDED UNGROUPING ACROSS CIRCUIT DESIGN HIERARCHYG06F 30/3323Filed as Synopsys, Inc.2025-04-16Eleonora TESTA | pending |
| DYNAMIC RESOURCE ALLOCATION FOR COMPUTATIONAL SIMULATIONG06F 30/23, G06F 9/50, G06F 9/5011, G06F 30/20, G06F2111/10, G06F 9/5027, G06F2209/505Filed as Synopsys Inc.2025-04-16Ian Campbell | pending |
| SCALABLE DISTRIBUTED ENVIRONMENT FOR RESET DOMAIN CROSSING ANALYSIS AND INTERACTIVE DEBUGG06F 30/33, G06F2119/12Filed as Synopsys, Inc.2025-04-04Abhishek Kumar | pending |
| MEMORY DEVICE WITH IMPROVED SENSING MARGIN AND LEAKAGE IMMUNITYH10B 12/00, H10B 12/01, H10D 62/102, H10D 62/151, H10D 64/251, G11C2211/4068Filed as Synopsys, Inc.2025-03-20Salvatore Maria Amoroso | pending |
| CLOCK AWARE SIMULATION VECTOR PROCESSORG06F 30/398, G06F 30/3308, G06F 30/3323, G06F2119/12, G06F 15/8053Filed as Synopsys, Inc.2025-03-05Ramesh NARAYANASWAMY | pending |
| MANAGING HIGH PERFORMANCE SIMULATION REPRESENTATION OF AN EMULATION SYSTEMG06F 11/3698, G06F 30/3308, G06F 30/327Filed as Synopsys, Inc.2025-02-14Ribhu Mittal | pending |
| POWER PERFORMANCE AREA OPTIMIZATION IN DESIGN TECHNOLOGY CO-OPTIMIZATION FLOWSFiled as SYNOPSYS, INC.2025-01-31WENWEN CHAI | pending |
| DETECTION OF MALICIOUS CIRCUITS INSERTED IN ANALOG CIRCUITSFiled as SYNOPSYS, INC.2025-01-17MAYUKH BHATTACHARYA | pending |
| ONE-TIME PROGRAMMABLE BITCELL FOR FRONTSIDE AND BACKSIDE POWER INTERCONNECTG11C 17/16, G11C 17/18Filed as Synopsys, Inc.2024-12-20Andrew Edward Horch | pending |
| METHOD TO REDUCE THE HARDWARE COSTS OF EXTRACTING POWER PROFILES IN EMULATION BY USING STATISTICAL TECHNIQUESFiled as SYNOPSYS, INC.2024-12-19BESHARA GEORGE ELMUFDI | pending |
| ONE-TIME PROGRAMMABLE BITCELL WITH A THERMALLY ENHANCED RUPTUREFiled as SYNOPSYS, INC.2024-12-16ANDREW EDWARD HORCH | pending |
| PREDICTION- BASED TERMINATION OF ANALOG CIRCUIT SIMULATIONSFiled as SYNOPSYS, INC.2024-12-13PEILIN JIANG | pending |
| INTEGRATED CIRCUIT DEVICE HAVING ROUTING WIRES WITH DIFFERENT WIDTH AND SHAPE FEATURESG06F 30/394Filed as Synopsys, Inc.2024-12-11Xu CHENG | pending |
| MULTI-ENVIRONMENT MODELING AND OPTIMIZATION FOR OPTICAL ASSEMBLIES WITH GENERAL HOUSINGSFiled as Synopsys, Inc.2024-11-27Eric M. SCHIESSER | pending |
| MACHINE-LEARNING-AIDED LOGIC SYNTHESIS USING DO-NOT-CARE-BASED BACKPROPAGATIONFiled as Synopsys, Inc.2024-11-18Yukio MIYASAKA | pending |
| ALIGNMENT MARKER ACQUISITION CIRCUITRY FOR A COMMUNICATION SYSTEMFiled as SYNOPSYS, INC.2024-11-14DENIS GEORGIEVICH POVERENNYY | pending |
| ADAPTIVE AND INCREMENTAL CIRCUIT DESIGN IMPLEMENTATIONFiled as SYNOPSYS, INC.2024-11-14SUDIPTO KUNDU | pending |
| Systems and Methods for Non-Parametric Optimization of Complex Shapes Using Neural Networks and Differentiable MorphingG06T 17/20, G06T 19/20, G06T2210/44, G06T2219/2021Filed as Synopsys, Inc.2024-11-14Louis Verret | pending |
| AUTOMATED TRANSLATION OF DESIGN SPECIFICATIONS OF ELECTRONIC CIRCUITSG06F 40/284, G06F 40/55, G06F 8/30, G06N 20/20, G06F 40/289, G06F 40/216, G06F 40/30, G06F 30/327, G06F 18/24323, G06N 3/09, G06F 18/214, G06N 3/045, G06N 3/0464, G06F 18/2431, G06N 3/044, G06N 3/0442, G01R 31/31704, G06F 8/427, G06F 11/3608, G06N 3/02, G06N 3/08Filed as Synopsys, Inc.2024-11-08Ganapathy Parthasarathy | pending |
| ASYNCHRONOUS SAR ADC WITH DETECTION AND CORRECTION CIRCUIT FOR LARGE AMPLITUDE OUTPUT CODE ERRORSH03M 1/462, H03M 1/0612, H03M 1/125, H03M 1/46, H03M 1/468Filed as Synopsys, Inc.2024-11-07Babak Zamanlooy | 12732206 |
| GENERATING VIOLATION WAIVERS FOR STATIC LINT CHECKG06F 11/3604, G06F 11/3608, G06F 8/41, G06F 8/427, G06F 8/433, G06F 8/75Filed as Synopsys, Inc.2024-11-05Tanu Aneja | pending |
| CHARACTERIZING PATH MARGIN MONITORS WITHOUT THE USE OF SCAN CHAINSFiled as SYNOPSYS, INC.2024-10-24GULVE ROHINI VASANT | pending |
| GRAPH-BASED VISUALIZATION OF WAYPOINT FOR DETECTING DESIGN ERROR IN INTEGRATED CIRCUIT DESIGNG06F 30/33, G06F 30/3323, G06F2111/10, G06F 30/327Filed as Synopsys, Inc.2024-10-18Subhadip Halder | pending |
| BITCELL POWER TRACKING SCHEME FOR TRANSIENT VOLTAGE COLLAPSE WRITE ASSISTG11C 11/417, G11C 11/419, G11C 5/14, G11C 5/144, G11C 5/147, G11C 7/12, G11C 7/227, G11C 11/412, G11C 11/418Filed as Synopsys, Inc.2024-10-18Che-Wei Wu | 12718877 |
| MEMORY ADDRESS CACHING FOR NEURAL NETWORKFiled as SYNOPSYS, INC.2024-10-17TOM MICHIELS | pending |
| INPUT/OUTPUT (IO) FAILSAFE PROTECTION TOPOLOGY IN LEAKY TECHNOLOGY NODESH03K 19/007, H03K 19/018521, G06F 11/0796, H03K 19/0013, H03K 19/0016, H03K 19/003, H03K 19/00315, H03K 19/00392Filed as Synopsys, Inc.2024-10-08Shailesh Kumar CHAUHAN | 12738940 |
| Hamming Distance Based Matching For PUF StringsH04L 9/3278, G09C 1/00, H04L 9/3234Filed as Synopsys, Inc.2024-09-27Geert Jan Schrijen | pending |
| CUSTOM LAYOUT RECOMMENDATION USING MACHINE LEARNINGFiled as SYNOPSYS, INC.2024-09-25SHABBIR BATTERYWALA | pending |
| LOW CONTENTION HIGH REFERENCE OFFSET TOLERANT LEVEL SHIFTERH03K 19/018507, H03K 19/018521, H03K 3/356017, H03K 3/356182, H03K 19/017509, H03K 19/0185Filed as Synopsys, Inc.2024-09-25Abhishek ROY | 12744532 |
| MEDIA ACCESS CONTROL (MAC) TO PHYSICAL CODING SUBLAYER (PCS) DATA RATE SYNCHRONIZATION CIRCUITRYH04L 12/40, H04L 43/0817, H04J 3/0697, H04L 1/0041, H04L 1/08, H04L 1/1657, H04L 7/041, H04L 25/4908Filed as Synopsys, Inc.2024-09-17Denis Georgievich POVERENNYY | 12580789 |
| RECURSIVE DOUBLING DECISION FEEDBACK EQUALIZERH04L 25/03057Filed as Synopsys, Inc.2024-09-13Helder Filipe Santana Campos | 12537723 |
| METHOD TO COMPUTE TIMING YIELD AND YIELD BOTTLENECK USING CORRELATED SAMPLE GENERATION AND EFFICIENT STATISTICAL SIMULATIONG06F 30/3312, G06F2111/08, G06F2119/22, G06F 30/337, G06F2119/12Filed as SYNOPSYS, INC.2024-09-03Jiayong LE | pending |
| IN SITU DELAY MEASUREMENTS ON INTEGRATED CIRCUITS USING LIVE DATA AND PULSE WIDTH MODULATIONFiled as SYNOPSYS, INC.2024-09-03KAREN DARBINYAN | pending |
| OPTICAL AND MANUFACTURING AWARE DESIGN FLOW FOR METASURFACESFiled as SYNOPSYS, INC.2024-08-30MARYVONNE CHALONY | pending |
| OPTICAL AND MANUFACTURING AWARE DESIGN FLOW FOR METASURFACESG02B 1/002, G02B 27/0012, G03F 7/0005Filed as Synopsys, Inc.2024-08-30Maryvonne CHALONY | pending |
| ADDING SCALAR BLINDING IN ELLIPTIC CURVE CRYPTOGRAPHYH04L 9/3066, G06F 7/725, H04L 9/003Filed as Synopsys, Inc.2024-08-14A. A. Jithra Adikari | 12732365 |
| COMBINED SERIAL AND CONCURRENT FAULT SIMULATIONG06F 30/327, G06F 11/261, G06F 30/33, G06F 11/221Filed as Synopsys, Inc.2024-08-12Ulrich HOLTMANN | pending |
| Voltage Scalable Fail-Safe IO DriversH03K 17/0822, H03K 17/102, H03K 19/00315, H03K 19/018521Filed as Synopsys, Inc.2024-08-08Ankit Agrawal | 12700860 |
| GENERATING HARDWARE DESCRIPTION LANGUAGE SLICES TO PROVIDE CONTEXT FOR VIOLATIONSG06F 30/323, G06F 30/32, G06F 30/33, G06F 30/3323, G06F 30/327, G06F 8/311Filed as Synopsys, Inc.2024-08-01Thanuja Madusanka | pending |
| SELF-LIMITING MANUFACTURING TECHNIQUES TO PREVENT ELECTRICAL SHORTS IN A COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET)H10D 84/038, H10W 20/034, H10D 84/0186, H10D 84/0195, H10D 84/017, H10D 88/01, H10W 20/40, H10W 20/069, H10W 20/20, H10W 20/0698, H10W 20/427, B82Y 10/00Filed as Synopsys, Inc.2024-07-31Xi-Wei LIN | pending |
Filings are matched to the company by applicant name, so a subsidiary filing under its own name is only here if that name resolves to this company. The applicant is printed as filed, which makes a wrong match visible. A patent is not a product: most applications are never granted, and most grants are never built.
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