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Cadence Design Systems Inc Patents
What Cadence Design Systems Inc has filed at the patent office — applications as well as grants, because a filing is on the record eighteen months before anyone has to say what it was for.
CDNS on carbonthat →Filings on file
32
Granted
31
Still pending
1
Filed under
1 names
32 filings
Newest filing first. A pending application has no patent number yet, and most never get one.
| Invention | Patent |
|---|---|
| EFFICIENT PHASE ENCODING FOR CLOCK RECOVERYH03K 5/135, H03K2005/00052, H03K2005/00286Filed as Cadence Design Systems, Inc.2025-01-13Satya Someswara Kaushik Yanamandra | 12658899 |
| DUAL-MODE RECEIVER TERMINATION DETECTION CIRCUITH04B 3/14, H04L 25/0272, H04B 3/46, H04L 25/0292, H04L 25/0298Filed as Cadence Design Systems, Inc.2025-01-02Satya Someswara Kaushik Yanamandra | 12652075 |
| CONTROL SIGNAL TRAININGG11C 8/18, G11C 29/028, G11C 7/1066, G11C 16/32, G11C 29/022, G11C 29/023, G11C 29/50012, G11C2207/2254Filed as Cadence Design Systems, Inc.2024-12-12Vinod Inipodu Murugan | 12744067 |
| HANDLING PHASE INTERPOLATOR INTEGRAL NON-LINEARITY ERRORS BASED ON PHASE ERROR MEASUREMENTSH03L 7/0814, H03L 7/093, H03L 7/0807, H03L 7/087Filed as Cadence Design Systems, Inc.2024-12-02Mark A. Summers | 12640743 |
| HYBRID PHASE INTERPOLATOR WITH UNIFIED BLENDER AND EYE-SURF CIRCUITH03K 5/135, H03K2005/00052Filed as Cadence Design Systems, Inc.2024-11-27Satya Someswara Kaushik Yanamandra | 12732174 |
| PARALLEL FAULT INJECTION BASED ON FUNCTIONAL INDEPENDENCEG06F 30/3308, G06F 11/261, G06F 30/33Filed as Cadence Design Systems, Inc.2024-11-22Joerg Mueller | 12650908 |
| LOOPBACK TEST FOR PHASE INTERPOLATOR CODESG01R 31/31727, H03L 7/0807, G01R 31/31724, H03L 7/07, H03L 7/0814, H03L 7/091, H03L 7/0998Filed as Cadence Design Systems, Inc.2024-11-21Mark A. Summers | 12730150 |
| ADC OFFSET CORRECTION WITH PARTIAL UNSCRAMBLED DATAH03M 1/1023, H04L 25/03019, H03L 7/0807Filed as Cadence Design Systems, Inc.2024-11-19Scott David Huss | 12739153 |
| APPLICATION-LEVEL DATA TRANSPORTATION IN DISTRIBUTED COMPUTING SYSTEMH04L 67/06, H04L 69/22Filed as Cadence Design Systems, Inc.2024-11-18Geoffrey Mark Furnish | 12615308 |
| DIGITAL EQUALIZATION ADAPTATION WITH PARTIALLY UNSCRAMBLED DATAH04L 25/03006, H04L 25/03885, H04L2025/03433, H04L2025/03745, H04L2025/03815Filed as Cadence Design Systems, Inc.2024-11-14Scott David Huss | 12640964 |
| ADC OFFSET DAC GLITCH SUPPRESSIONH03M 1/0607, H03M 1/0863Filed as Cadence Design Systems, Inc.2024-11-13Chunkyun Seok | 12738950 |
| SAR ADC BIT STORAGE UPON RESETH03M 1/462, H03M 1/466, H03M 1/42, H03M 1/46Filed as Cadence Design Systems, Inc.2024-11-13Christopher George Moscone | 12726211 |
| DECISION FEEDBACK EQUALIZATION TRAINING FOR SINGLE-ENDED RECEIVERH04L 25/03057, H04L 25/03146, H04L 25/03885, H04L2025/03592Filed as Cadence Design Systems, Inc.2024-10-09Hari Anand Ravi | 12676777 |
| REDUCTION OF BANDGAP VOLTAGE VARIATION IN AN INTEGRATED CIRCUITG05F 1/56, G05F 1/46, G05F 3/30Filed as Cadence Design Systems, Inc.2024-10-08Arun Goyal | 12669838 |
| System and Method for Automatic Data Library Creation Associated with an Electronic DesignG06F 30/31, G06F2111/20Filed as Cadence Design Systems, Inc.2024-09-27Hanish Wadhawan | pending |
| MULTI-TAP DECISION FEEDBACK EQUALIZER (DFE) TRAINING IN A MEMORY PHYSICAL (PHY) LAYERH04L 25/03267, H04L 25/03057, H04L 25/03146, H04L 25/03885, H04L2025/03636Filed as Cadence Design Systems, Inc.2024-08-06Anirudha Anil Shelke | 12671612 |
| SELF-CORRECTING PATTERN DETECTION ARCHITECTUREG01R 31/3187Filed as Cadence Design Systems, Inc.2024-07-30Ashish Agrawal | 12730151 |
| SAMPLER CIRCUIT WITH LOW DEADBAND ACROSS PROCESS, VOLTAGE, AND TEMPERATUREH03M 1/002, H03M 1/742, H03F 3/45475, H03F2200/261Filed as Cadence Design Systems, Inc.2024-06-21Hajee Mohammed Shuaeb Fazeel | 12647127 |
| GLITCH-FREE DELAY LINE ARCHITECTUREH03K 5/134, H03K 5/135, G11C 7/222, G11C 11/4076, H03K2005/00195, H03L 7/0814, H03L 7/0818Filed as Cadence Design Systems, Inc.2024-06-07Parth Manishbhai Dodiya | 12640718 |
| COMMON MODE SHIFTING OF SINGLE-ENDED SIGNALS BASED ON LINEARITY ANALYSISG11C 11/4093, H03F 3/45183, H03F 3/45475, H03K 19/017509Filed as Cadence Design Systems, Inc.2024-05-17Ashwin S.M. | 12548616 |
| PROGRAMMABLE CIRCUIT TO CANCEL FREQUENCY DRIFTH03K 3/011, H03K 17/6871Filed as Cadence Design Systems, Inc.2024-04-18Amit Katyal | 12537514 |
| DYNAMIC SWITCHING ARCHITECTURE FOR HIGH VOLTAGE APPLICATIONSH03K 17/6872Filed as Cadence Design Systems, Inc.2024-04-05Vipul Jain | 12633915 |
| SUBRANGING DIGITAL TO TIME CONVERTER-BASED FRACTIONAL PHASE LOCKED LOOP ARCHITECTUREH03L 7/0992, H03L 7/1976, H03L 7/081, H03L 7/0891, H03L 7/091, H03L2207/50Filed as Cadence Design Systems, Inc.2024-04-02Sudipta Sarkar | 12603655 |
| FLOATING TAP PARTIALLY ROLLED DIGITAL FEEDBACK EQUALIZATION ARCHITECTUREH04L 25/03057, H04L 25/03885, H04L2025/0349, H04L2025/03579Filed as Cadence Design Systems, Inc.2024-03-29Shikha Rani | 12683835 |
| HYBRID-EMPHASIS EQUALIZATION CIRCUITH04L 25/03038, H04L 25/03343, H04L 25/03878, H04L 25/03885, H04L 25/4917Filed as Cadence Design Systems, Inc.2024-03-20Vinod Kumar | 12676776 |
| PHASE LOCKED LOOP ARCHITECTURE WITH REDUCED BANDWIDTH VARIATIONH03L 7/0891, H03L 7/093, H03L 1/02, H03L 7/0991Filed as Cadence Design Systems, Inc.2024-03-18Shaojun Ma | 12609706 |
| EYE WIDTH SWEEP TEST FOR USE IN DATA TRANSMISSIONH04L 1/0041, H04L 1/0061Filed as Cadence Design Systems, Inc.2024-03-07Satish Kumar Ambati | 12732303 |
| CLOCK GATINGG06F 1/12, G06F 1/3237Filed as Cadence Design Systems, Inc.2024-03-07Kandregula Uma Suri Appa Rao | 12541223 |
| LFPS PULSE DETECTION USING UNIT INTERVAL ADJUSTMENT BASED ON AVERAGE PULSE WIDTHH03K 21/40, H03K 7/08, H03K 21/38Filed as Cadence Design Systems, Inc.2024-03-05Xiaoyang Liu | 12483248 |
| VERIFICATION OF DATA COMMUNICATION SPECIFICATION USING SEQUENCE NUMBER-BASED MONITOR SYNCHRONIZATIONH04L 43/20, H04L 43/50, H04L 1/1642, H04L 1/1822Filed as Cadence Design Systems, Inc.2024-02-19Pedro Eugenio Medeiros | 12348403 |
| SIGNAL RECEIVER WITH ADAPTIVE STROBE GATING AND REDUCED POWER DATAPATH ARCHITECTUREG11C 7/222, G11C 7/1087, G11C 7/1093, G11C 29/52Filed as Cadence Design Systems, Inc.2024-01-25Anirudha Shelke | 12548608 |
| POWER CONSUMPTION ESTIMATION OF MEMORY UNDER TESTG06F 1/28, G11C 29/36Filed as Cadence Design Systems, Inc.2024-01-05Puneet Arora | 12393246 |
Filings are matched to the company by applicant name, so a subsidiary filing under its own name is only here if that name resolves to this company. The applicant is printed as filed, which makes a wrong match visible. A patent is not a product: most applications are never granted, and most grants are never built.
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