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Astera Labs, Inc Patents

What Astera Labs, Inc has filed at the patent office — applications as well as grants, because a filing is on the record eighteen months before anyone has to say what it was for.

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Filings on file
18
Granted
10
Still pending
8
Filed under
2 names

18 filings

Newest filing first. A pending application has no patent number yet, and most never get one.

InventionPatent
THERMAL INTERFACE MATERIAL UNIFORMITY SYSTEM AND METHOD OF OPERATION THEREOFFiled as ASTERA LABS, INC.2025-08-19ZUNHANG YU KASNAVIpending
PLUGGABLE RETIMER MODULEH01R 12/75, G06F 13/409, H01R 12/721, H01R 12/737, H01R2201/06Filed as Astera Labs, Inc.2025-06-10Christopher Blackburnpending
THERMAL INTERFACE MATERIAL UNIFORMITY SYSTEM AND METHOD OF OPERATION THEREOFH10W 40/00Filed as Astera Labs, Inc.2025-02-06Zunhang Yu KASNAVIpending
Smart Cable with Heterogenous Primary/Sideband Communication ChannelsG06F 13/4022, G06F 13/4027, G06F 13/4068Filed as Astera Labs, Inc.2024-12-12Pulkit Khandelwal12754866
Signaling Trace with Width-Modulated Discontinuity MitigationH05K 1/0219, H05K 1/0245, H05K 1/0296, H05K 1/025, H05K 3/00, H05K 3/0005, H05K 3/06, H05K2201/09263Filed as Astera Labs, Inc.2024-12-12Alexander Franckpending
MEMORY CONTROL COMPONENT WITH SPLIT AUXILIARY CHANNELG06F 11/1004, G06F 11/1048Filed as Astera Labs, Inc.2024-10-11Anh T. Tran12724667
Smart Cable with Heterogenous Primary/Sideband Communication ChannelsFiled as Astera Labs, Inc.2024-08-27Pulkit Khandelwalpending
Signaling Trace with Width-Modulated Discontinuity MitigationFiled as Astera Labs, Inc.2024-08-26Alexander Franckpending
THERMAL INTERFACE MATERIAL UNIFORMITY SYSTEM AND METHOD OF OPERATION THEREOFFiled as Astera Labs, Inc.2024-08-26Zunhang Yu KASNAVIpending
VIRTUAL METADATA STORAGE WITH DECODE-ALIAS MITIGATIONG06F 11/1012, G06F 11/1068, G06F 11/1004Filed as Astera Labs, Inc.2024-08-12Jitendra Mohan12596612
CXL HDM DECODING SEQUENCING FOR REDUCED AREA AND POWER CONSUMPTIONG06F 3/0625, G06F 3/0679, G06F 1/3275, G06F 3/0655, G06F 12/109, G06F2212/65Filed as Astera Labs, Inc.2024-07-22Enrique MUSOLL12579076
Cable Interconnect with Integrated Retimer/GearboxFiled as Astera Labs, Inc.2024-06-14Christopher Blackburnpending
METADATA-CACHING INTEGRATED CIRCUIT DEVICEG06F 12/0802, G06F 12/0895, G06F2212/45, G06F2212/466Filed as Astera Labs, Inc.2024-06-04Enrique Musoll12730751
Configurable-Aggregation Retimer With Lane-Dedicated ControllersG06F 13/4295, H04L 7/0041, G06F 13/4291, G06F2213/0026, H04L 7/033, H04L 25/03885Filed as Astera Labs, Inc.2024-05-02Enrique Musoll12542646
INTERLOCKING STRUCTURE FOR CROSSTALK REDUCTION AND METHOD OF MANUFACTUREH10W 70/685, H05K 1/0224, H10W 90/701, H10W 90/724, H10W 42/20, H05K 1/0216, H05K 1/0218, H05K 1/0219, H05K 1/181, H05K 3/341, H05K 3/3436, H05K 3/4602, H05K2201/0723Filed as Astera Labs, Inc.2024-04-30Abhinaya Easwari MOHAN12652750
EARLY POTENTIAL HPA GENERATORG06F 12/0646, G06F 12/109, G06F 3/0656, G06F 3/0659, G06F 12/063, G06F 12/0835, G06F 12/0868, G06F 12/1027, G06F 12/1072, G06F2212/1008, G06F2212/1016, G06F2212/1024, G06F2212/151, G06F2212/154, G06F2212/651, G06F2212/657, G06F2212/7201Filed as Astera Labs, Inc.2024-04-18Enrique MUSOLL12505039
RETIMER WITH PATH-COORDINATED FLOW-RATE COMPENSATIONG06F 13/405, H04L 5/0083, G06F 13/4291, G06F2213/0026, H04L 1/0007, H04L 1/0057, H04L 5/0087, H04L 25/14Filed as Astera Labs, Inc.2024-02-28Enrique Musoll12489590
Retimer With Host-Interactive Data Logging EngineG06F 9/4881, G06F 9/30036, G06F 9/3005, G06F 9/3836, G06F 9/544Filed as Astera Labs, Inc.2024-02-26Ken (Keqin) Han12327135

Filings are matched to the company by applicant name, so a subsidiary filing under its own name is only here if that name resolves to this company. The applicant is printed as filed, which makes a wrong match visible. A patent is not a product: most applications are never granted, and most grants are never built.

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